Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog

Abstract:

As a first step, most model checkers used in the hardware industry convert a high-level register-transfer-level (RTL) design into a netlist. However, algorithms that operate at the netlist level are unable to exploit the structure of the higher abstraction levels and, thus, are less scalable. The RTL of a hardware description language such as Verilog is similar to a software program with special features for hardware design such as bit-vector arithmetic and concurrency. This paper uses predicate abstraction, a software verification technique, for verifying RTL Verilog. There are two challenges when applying predicate abstraction to circuits: 1) the computation of the abstract model in presence of a large number of predicates and 2) the discovery of suitable word-level predicates for abstraction refinement. We address the first problem using a technique called predicate clustering. We address the second problem by computing the weakest preconditions of Verilog statements in order to obtain new word-level predicates during abstraction refinement. We compare the performance of our technique with localization reduction, a netlist-level abstraction technique, and report improvements on a set of benchmarks.

• BibTex

@article { JainKSC08,
	title = {Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog},
	journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
	volume = {27},
	number = {2},
	year = {2008},
	pages = {366-379},
	author = {Himanshu Jain and  Daniel Kroening and  Natasha Sharygina and  Edmund M. Clarke}
}